Unified theory to build cell-level transistor networks from BDDs [logic synthesis]

This paper presents a unified theory to build transistor networks through binary decision diagrams - BDDs. It is able to obtain transistor networks with transistor count near to the best case of other methods presented in the literature. As a result, a pass transistor network implementation is automatically generated for XOR-like gates, since static CMOS performs badly. Similarly, a static CMOS topology is preferred for the generation of NAND-like gates, on which pass transistor logic is not optimal. Variations on the derivation of transistor networks from BDDs are extensively discussed.