Channel and source/drain engineering in high-performance sub-0.1 /spl mu/m NMOSFETs using X-ray lithography

Channel lengths are continually scaled to smaller dimensions to improve performance and packing density. In recent years this has led to demonstrations of MOSFETs with effective channel length of 0.1 /spl mu/m and below. The key technology challenges at these linewidths include the lithography to reproducibly achieve fine dimensions, source and drain engineering to reduce device parasitics, and channel engineering to control short-channel effects. In this work, we demonstrate a high-performance NMOS technology that utilizes X-ray lithography to achieve channel lengths below 0.1 /spl mu/m; a novel cobalt salicidation (CoSi/sub 2/) technique using a titanium/cobalt laminate to achieve very low parasitic source/drain resistance; and shallow junctions and an optimized super-steep retrograde (SSR) channel profile to achieve very high transconductance devices with excellent control of short-channel effects.<>