Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs

Author

Mizuno, T. ; Iwase, M. ; Niiyama, H. ; Shibata, T. ; Fujisaki, K. ; Nakasugi, T. ; Toriumi, A. ; Ushiku, Y.

Author_Institution

ULSI Res. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

7-9 June 1994

Firstpage

13

Lastpage

14

Abstract

The authors have recently demonstrated that 0.1 /spl mu/m gate length CMOS devices normally operate at room temperature. Moreover, they have experimentally shown that the threshold voltage of MOSFETs fluctuates due to the statistical fluctuations of channel dopant number, n/sub a/, which increases by reducing the gate length. Even if the individual 0.1 /spl mu/m MOSFETs operate normally, can one succeed in fabricating 0.1 /spl mu/m region ULSIs without failure ? To obtain the answer, it is necessary to study the performance fluctuations of 0.1 /spl mu/m region MOSFETs. This paper discusses the peculiar fluctuations of the threshold voltage and the transconductance of 0.10 /spl mu/m gate length NMOSFETs, using an 8 k MOSFET array and mentions their physical mechanism. Finally, the performance fluctuations of 0.1 /spl mu/m region ULSIs are estimated.<>

Keywords

CMOS integrated circuits; VLSI; insulated gate field effect transistors; 0.1 micron; CMOS devices; MOSFET; NMOSFETs; ULSI; channel dopant; gate length; performance fluctuations; threshold voltage; transconductance; CMOS process; FETs; Fluctuations; Frequency; Lithography; MOSFET circuits; Temperature; Transconductance; Ultra large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324401

Filename

324401