Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

Presents a simple architecture achieving high-speed serial read/write operations as an additional function mode for low-cost standard DRAMs (dynamic random-access memories). In the architecture, an on-chip double-bank interleaved data processing scheme is coupled with a preceding column selecting method, and consequently a twice-higher bandwidth than that in a conventional fast-page mode can be obtained with a few extra circuits. Implementing the architecture on an experimental 64-Mb DRAM, sub-10-ns serial access has been demonstrated with only a 3% area penalty