DocumentCode
2090752
Title
A new hybrid parallel/reconfigurable architecture: the X4CP32
Author
Azevedo, Arnaldo ; Soares, Rodrigo ; Silva, Ivan Saraiva
fYear
2003
fDate
8-11 Sept. 2003
Firstpage
225
Lastpage
230
Abstract
This paper describes a new kind of general-purpose microprocessor: the hybrid runtime reconfigurable/parallel X4CP32. It consists of 2 programming levels, based on a hierarchic array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfiguration and programming, which is its main strength. Although it is effective in heavy arithmetic applications, it is suited for virtually any task an application can demand, presenting a solid option for a general-purpose microprocessor.
Keywords
microprocessor chips; parallel architectures; reconfigurable architectures; X4CP32; arithmetic applications; general-purpose microprocessor; hybrid parallel/reconfigurable architecture; reconfigurable entities hierarchic array; runtime programming; runtime reconfigurable; Hybrid integrated circuits; Reconfigurable architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on
Print_ISBN
0-7695-2009-X
Type
conf
DOI
10.1109/SBCCI.2003.1232833
Filename
1232833
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