On-chip decoupling capacitor optimization for noise and leakage reduction

On-chip decoupling capacitors are widely used in today´s high-performance microprocessor design to mitigate the power supply noise problem. The continued reduction of oxide thickness in advanced nanotechnology, however, also significantly increases the tunneling current and leakage power of thin-oxide capacitors. This paper describes the modeling and simulation of a complete chip and package power supply distribution network, and the optimization of the placement of thin-oxide and thick-oxide capacitors to reduce the tunneling current, leakage power, and burn-in cost, while limiting the power supply noise within a noise margin.