Title :
A 288-kbit fully parallel content addressable memory using stacked capacitor cell structure
Author :
Yamagata, Tadato ; Mihara, Masaaki ; Hamamoto, Takeshi ; Kobayashi, Toshifumi ; Yamada, Michihiro
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The authors describe a 288-kb (8 K words×36-b) fully parallel CAM (content addressable memory) LSI using a compact dynamic CAM cell (66 μm2) with stacked capacitor structure and a novel hierarchical priority encoder. The chip size is 10.3×12.0 mm 2, and the typical cycle time is 150 ns using circuit simulation. This CAM LSI performs large-scale search operations very efficiently, and therefore has the possibility of broad applications to high-performance artificial-intelligence machines and relational database systems
Keywords :
CMOS integrated circuits; content-addressable storage; integrated memory circuits; large scale integration; parallel architectures; 0.8 micron; 150 ns; 288 kbit; LSI; artificial-intelligence machines; compact dynamic CAM cell; content addressable memory; double metal CMOS process; fully parallel; hierarchical priority encoder; large-scale search operations; relational database systems; stacked capacitor cell structure; Application software; Artificial intelligence; Associative memory; CADCAM; Capacitance; Capacitors; Circuits; Computer aided manufacturing; Large scale integration; Research and development;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164123
