A large scale FPGA with 10 K core cells with CMOS 0.8 μm 3-layered metal process

Author

Muroga, H. ; Murata, H. ; Saeki, Y. ; Hibi, T. ; Ohashi, Y. ; Noguchi, T. ; Nishimura, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

A large-scale FPGA (field-programmable gate array) that contains 10 K core cells is described. The core cell, a programmable logic module, consists of a two-input NAND gate, a latch circuit, and bus drivers. The function of one core cell is estimated to be equivalent to four NAND gates. As a result, the FPGA integrates a total of 40 K gates. Configuration data are stored in SRAMs on the device. A booster circuit on the chip supplies higher voltage to reduce on-resistance of the switch elements to ensure high-speed operation. This FPGA has two programming modes, the BFR (boot from ROM) mode, in which the FPGA accesses outer nonvolatile memory devices, and the CPU mode, which is controlled by a CPU as a peripheral device. A probe system is implemented on the device to read the output signal of each core cell to realize swift debugging of configured circuits

Keywords

CMOS integrated circuits; logic arrays; 0.8 micron; CPU mode; SRAMs; booster circuit; boot from ROM; bus drivers; core cells; debugging; field-programmable gate array; high-speed operation; large scale FPGA; latch circuit; probe system; programmable logic module; programming modes; three-layered metal process; two-input NAND gate; CMOS logic circuits; Central Processing Unit; Field programmable gate arrays; Large-scale systems; Latches; Logic circuits; Logic devices; Programmable logic arrays; Programmable logic devices; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164125

Filename

164125