Improving critical path identification in functional timing analysis

True critical path identification is still an issue of relevant importance in the physical design of CMOS VLSI circuits. Although delay enumeration-based timing analysis methods are independent of the number of long false paths, they are not able to identify the true critical paths of a combinational block. Hence, path enumeration-based timing analysis must be used. In this paper, we present a new heuristic for ordering the objectives that need to be satisfied for declaring a path as sensitizable. The new heuristic is compared to the commonly used one, which relies on following the logical depth of the circuit. The practical results showed that the proposed heuristic tends to provide better results.