A transistor sizing method applied to an automatic layout generation tool

This paper presents a method of transistor sizing, integrated to a row-based automatic layout generation tool. Automatic layout generation is able to generate a more optimized layout in relation to the standard cell approach because standard cell libraries present a limited number of cells. Most transistor sizing algorithms propose continuous sizing according to the performance constraints and hence cannot be applied in row-based layouts. In this paper, transistors are folded to keep the row height, discretely sizing the transistor. In order to save the final area of the circuit, only transistors in the longest sensitizable paths are sized. The efficiency of the algorithm is measured in relation to area and delay.