Title :
Memory chip for 24-port global register file
Author :
Maly, W. ; Patyra, M. ; Primatic, A. ; Raghavan, V. ; Storey, T. ; Wolfe, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
The design of 256×32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental, CMOS implementation of this SRAM chip are reported in detail
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; 32 bit; 8 kbit; CMOS; design tradeoffs; global register file; multiport SRAM chip; performance measurements; static random-access memory; CMOS technology; Concurrent computing; Data processing; Delay; Measurement; Parallel processing; Program processors; Random access memory; Registers; SRAM chips;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164130
