A 80 MFLOPS 64-bit microprocessor for parallel computer

Author

Nakano, Hiraku ; Nakajima, Masaitsu ; Nakakura, Yasuhiro ; Yoshida, Tadahiro ; Goi, Yoshiyuki ; Nakai, Yuji ; Segawa, Reiji ; Kishida, Takeshi ; Kadota, Hiroshi

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle simultaneously. The processor, implemented in a 0.8-μm CMOS technology, contains 1300 K transistors. The processor also employs a RISC (reduced instruction set computer) architecture and Harvard-style bus organization. Division is accomplished every 200 ns. A typical performance is 64 MFLOPS

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; microprocessor chips; parallel architectures; 0.8 micron; 200 ns; 25 ns; 64 bit; 80 MFLOPS; CMOS; Harvard-style bus organization; RISC; parallel computer; reduced instruction set computer; superscalar architecture; two instruction parallel architecture; Buffer storage; Computer aided instruction; Concurrent computing; Data flow computing; Decoding; Digital arithmetic; Floating-point arithmetic; Microprocessors; Pipelines; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164132

Filename

164132