A pass transistor design methodology for 256 Mbit DRAM and beyond

Author

Chatterjee, A. ; Liu, J. ; Mozumder, P.K. ; Rodder, M. ; Chen, I.-C.

Author_Institution

Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

7-9 June 1994

Firstpage

137

Lastpage

138

Abstract

A novel pass transistor design methodology to optimize gate oxide thickness (t/sub ox/), booted wordline voltage (V/sub WL/), substrate bias (V/sub sub/), and processing conditions is presented in this paper. It is found that for a gate length of 0.3 /spl mu/m a t/sub ox/ of about 85 /spl Aring/ (which is much thicker than the /spl sim/65 /spl Aring/ t/sub ox/ for 0.25 /spl mu/m logic technology) to support a V/sub WL/ of 3.75 V, a V/sub sub/ of about -1 V, and As LDD are the optimum technological choices for 256 Mbit DRAM.<>

Keywords

DRAM chips; MOS integrated circuits; VLSI; insulated gate field effect transistors; integrated circuit technology; 0.3 micron; 256 Mbit; 3.75 V; 85 angstrom; DRAM; LDD; booted wordline voltage; gate length; gate oxide thickness; pass transistor design methodology; processing conditions; substrate bias; Capacitors; Design methodology; Design optimization; Implants; Isolation technology; Logic; Random access memory; Substrates; Subthreshold current; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324419

Filename

324419