Title :
A 1.5 MLIPS 40-bit AI processor
Author :
Machida, Hirohisa ; Ando, Hideki ; Ikenaga, Chikako ; Nakashima, Hiroshi ; Maeda, Atsushi ; Nakaya, Masao
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A high-performance 40-bit AI (artificial intelligence) processor with a capability of 1.5 MLIPS (mega-logical-inference per second) in append has been developed. The performance of this processor is achieved by the combination of novel architectures of pipelined data typing and dereference, a 0.8-μm CMOS technology, and a clock scheme
Keywords :
CMOS integrated circuits; VLSI; artificial intelligence; microprocessor chips; pipeline processing; symbol manipulation; 1.5 MLIPS; 40 bit; CMOS; append; artificial intelligence processor; clock scheme; data typing; dereference; performance; pipeline architecture; Artificial intelligence; CMOS technology; Clocks; Decoding; Electrostatic precipitators; Hardware; Logic programming; Natural languages; Pulse width modulation; Workstations;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164135
