Title :
A new capacitor on metal (COM) cell for beyond 256 Mbit DRAM
Author :
Yoon, J.Y. ; Han, D.H. ; Noh, J.Y. ; Kwon, K.W. ; Park, Y.W. ; Chung, U.I. ; Lee, W.S. ; Choi, C.S. ; Hwang, C.G.
Author_Institution :
Adv. Technol. Center, Samsung Electron. Co. Ltd., Kyungki, South Korea
Abstract :
We propose an advanced DRAM cell structure with a capacitor formed after patterning the first-level metal. Since the second-level-metal which will be patterned after forming storage capacitors usually has a relaxed design rule, a sufficient cell capacitance can be obtained in this structure by simply increasing the stack height of the capacitor. A limited thermal cycle after the storage node formation makes it possible to use Ta/sub 2/O/sub 5/ as a dielectric material without causing high temperature related leakage problems.<>
Keywords :
DRAM chips; VLSI; cellular arrays; integrated circuit technology; 256 Mbit; COM cell; DRAM; Ta/sub 2/O/sub 5/; capacitor on metal cell; cell capacitance; cell structure; dielectric material; limited thermal cycle; second-level-metal; stack height; storage node formation; Capacitance; Capacitors; Costs; Dielectric materials; Leakage current; Material storage; Planarization; Random access memory; Temperature; Tungsten;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324420
