A multi-speed digital cross-connect switching VLSI using new circuit techniques in dual port RAMs

Author

Shinagawa, Satoshi ; Satoh, Yoichi ; Mizukami, Masao ; Sonobe, Yasuo ; Nakano, Yukio ; Kanno, Tadayuki

Author_Institution

Hitachi VLSI Eng. Co., Ltd., Tokyo, Japan

fYear

1991

fDate

12-15 May 1991

Abstract

The authors describe a multi-speed digital cross-connect switching VLSI using innovative circuit techniques in dual port RAMs, and adopting 0.8-μm CMOS technology. The five embedded dual port RAMs (four 1 kw×9 b, one 256 w×18 b) each achieved an access-time of 3.7 ns and 100-mW power consumption at 38.88-MHz operation. A block diagram of the VLSI is presented, the chip features are described, and the characteristics of the RAMs are summarized

Keywords

CMOS integrated circuits; VLSI; digital communication systems; digital integrated circuits; random-access storage; switching circuits; switching systems; 0.8 micron; 100 mW; 3.7 ns; 38.88 MHz; 4608 bit; 9 kbit; CMOS technology; SDH networks; access-time; digital cross-connect switching; dual port RAMs; embedded RAM; multispeed type; power consumption; switching VLSI; synchronous digital hierarchy; CMOS technology; Clocks; Energy consumption; Random access memory; Read-write memory; Road transportation; Switches; Switching circuits; Synchronous digital hierarchy; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0015-7

Type

conf

DOI

10.1109/CICC.1991.164137

Filename

164137