Title :
A Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond
Author :
Maeda, Shigenobu ; Maegawa, Shigeto ; Ipposhi, Takashi ; Nishimura, Hideki ; Kuriyama, H. ; Tanina, O. ; Inoue, Yasuyuki ; Nishimura, Hideki ; Tsubouchi, N.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
We propose a Vertical /spl Phi/-shape Transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek alphabet /spl Phi/. It is built by penetration of the gate electrode (=word line) which has been formed beforehand. Application of the V/spl Phi/T for DRAM cell brings about cell size reduction to 50% and process simplification of about 10% at least. This is mainly because its bit line contact and the V/spl Phi/T are vertically aligned and storage node contact is eliminated. We have indicated that the V/spl Phi/T is an interesting candidate for the gigabit DRAM in view of size, cost and performance.<>
Keywords :
DRAM chips; MOS integrated circuits; cellular arrays; insulated gate field effect transistors; integrated circuit technology; 1 Gbit; bit line contact; cell size reduction; gate electrode; gigabit DRAM; process simplification; storage node contact; vertical /spl Phi/-shape transistor cell; vertical MOSFET; Boron; Costs; Crystallization; Electrodes; Fabrication; Insulation; Laboratories; Oxidation; Parasitic capacitance; Random access memory;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324421
