Title :
Design methodology of a 200 MHz superscalar macroprocessor: SH-4
Author :
Hattori, Toshihiro ; Nitta, Yusuke ; Seki, Mitsuho ; Narita, Susumu ; Uchiyama, Kunio ; Takahashi, Tsuyoshi ; Satomura, Ryuichi
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A new design methodology focusing on high speed operation and short design time is described for the SH-4 200 MHz superscalar microprocessor. Random test generation, logic emulation, and formal verification are applied to logic verification for shortening design time. Delay budgeting, forward/back annotation, and clock design are key features for timing driven design.
Keywords :
formal verification; logic CAD; logic testing; microprocessor chips; 200 MHz superscalar macroprocessor; SH-4; clock design; delay budgeting; design methodology; formal verification; forward/back annotation; logic emulation; logic verification; random test generation; timing driven design; Clocks; Delay estimation; Design methodology; Large scale integration; Logic design; Logic testing; Microprocessors; Permission; Power dissipation; Timing;
Conference_Titel :
Design Automation Conference, 1998. Proceedings
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-89791-964-5
