DocumentCode :
2091536
Title :
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture
Author :
Adimulam, Mahesh Kumar ; Veeramachaneni, Sreehari ; Muthukrishnan, N. Moorthy ; Srinivas, M.B.
Author_Institution :
Dept. of ECE, Birla Inst. of Technol. & Sci. Pilani, Hyderabad, India
fYear :
2010
fDate :
5-7 July 2010
Firstpage :
434
Lastpage :
435
Abstract :
In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply voltage of 1.0V, it consumes 48 mW at 8-bit, 36 mW at 6-bit and 15 mW at 4-bit resolution. The proposed ADC have been designed, compared with conventional flash ADC and verified for post layout simulations in standard 65 nm CMOS technology.
Keywords :
CMOS integrated circuits; analogue-digital conversion; flash memories; integrated circuit design; low-power electronics; CMOS technology; low power flash ADC; sub flash architecture; variable resolution flash ADC; CMOS integrated circuits; Multiplexing; Power demand; Resistors; Signal resolution; Signal to noise ratio; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location :
Lixouri, Kefalonia
Print_ISBN :
978-1-4244-7321-2
Type :
conf
DOI :
10.1109/ISVLSI.2010.68
Filename :
5572828
Link To Document :
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