Cornerless active area cell and Bi-T-MOS process for sub-half micron SRAMs

Author

Ishida, M. ; Kuriyama, H. ; Tsutsumi, K. ; Ipposhi, T. ; Kohno, Y. ; Miyoshi, H.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1994

fDate

7-9 June 1994

Firstpage

103

Lastpage

104

Abstract

This paper presents a novel memory cell and process technology. The memory cell adopts the symmetry layout which has cornerless active area, a single bent word line and common gate TFTs. Furthermore, this memory cell realizes large cell ratio using a direct contact off-set resistance. The proposed process technology is optimization of bipolar, TFT and CMOS process (Bi-T-MOS). The Bi-T-MOS technology decreases the poly-silicon layers to triple-level without decreasing performance of the transistors.<>

Keywords

BiCMOS integrated circuits; SRAM chips; cellular arrays; integrated circuit technology; thin film transistors; Bi-T-MOS process; cell ratio; common gate TFTs; cornerless active area cell; direct contact off-set resistance; memory cell technology; polysilicon layers; process technology; single bent word line; sub-half micron SRAMs; symmetry layout; triple-level layers; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Contact resistance; Driver circuits; Electrodes; Oxidation; Random access memory; Silicon; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324434

Filename

324434