Reed-Solomon Codec for a Reconfigurable Baseband Processing Platform

Author

Yang, Qingqing ; Zhou, Xiaofang ; Sobelman, Gerald E.

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2009

fDate

24-26 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents the VLSI design of a multi-mode Reed-Solomon codec. Our decoder design is based on the modified Euclidean (ME) algorithm and shares hardware between the ME algorithm and the computation part of the Chien search. With its ability to support a variety of RS(n, k, t) code parameters (0 les n les 255), (0 les t les 8) as well as different finite fields GF(2^m), (3 les m les 8), this RS codec design is suitable for use in a reconfigurable baseband processing platform. Synthesis results indicate that this codec operates at a maximum frequency of 177 MHz and has a peak data processing rate of 1416 Mbps.

Keywords

Reed-Solomon codes; VLSI; codecs; software radio; Chien search; RS codec design; Reed-Solomon codecs; VLSI design; data processing rate; decoder design; frequency 177 MHz; modified Euclidean algorithm; reconfigurable baseband processing platform; wireless communication; Algorithm design and analysis; Baseband; Codecs; Data processing; Decoding; Frequency synthesizers; Galois fields; Hardware; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2009. WiCom '09. 5th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3692-7

Electronic_ISBN

978-1-4244-3693-4

Type

conf

DOI

10.1109/WICOM.2009.5301729

Filename

5301729