Title :
Trench isolation technology with 1 /spl mu/m depth n- and p-wells for a full-CMOS SRAM cell with a 0.4 /spl mu/m n/sup +p/sup +/ spacing
Author :
Ishimaru, Kazuhisa ; Gojohbori, H. ; Koike, H. ; Unno, Y. ; Sai, M. ; Matsuoka, F. ; Kakumu, M.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
This paper shows that 0.7 /spl mu/m depth shallow trench isolation with SiO/sub 2/ filling can achieve 0.4 /spl mu/m n+/p+ spacing, utilizing shallow p- and n-wells formation with retrograde profiles. An 80 degree taper trench with rounded edge accompanied by HCl ambient oxidation improves subthreshold characteristics and junction leakage. A 7.65 /spl mu/m/sup 2/ full-CMOS cell competitive to TFT cell size at 0.35 /spl mu/m design rule has been realized and a 256k bit SRAM has been fabricated.<>
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit technology; oxidation; 0.35 /spl mu/m design rule; 0.4 mum; 0.7 mum; 1 /spl mu/m depth; 1 mum; 256 kbit; 256k bit SRAM; HCl; HCl ambient oxidation; SiO/sub 2/ filling; TFT cell size; full-CMOS SRAM cell; full-CMOS cell; junction leakage; n-wells; n/sup +p/sup +/ spacing; p-wells; retrograde profiles; rounded edge; shallow trench isolation; subthreshold characteristics; taper trench; trench isolation technology; Etching; Impurities; Isolation technology; Leakage current; Planarization; Random access memory; Shape; Thin film transistors; Threshold voltage; Very large scale integration;
Conference_Titel :
VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-1921-4
DOI :
10.1109/VLSIT.1994.324437
