Title :
A Family of Area-Time Efficient Modulo 2n+1 Adders
Author_Institution :
Comput. Eng. & Inf. Dept, Univ. of Patras, Rio, Greece
Abstract :
A family of diminished-1 modulo 2n+1 adders is proposed in this manuscript. All members of the family use a sparse carry computation unit for deriving only some of the carries in log2n prefix levels, while all the rest carries are computed in an extra one. The proposed adders offer significant area and power savings compared to earlier proposals, while maintaining a high operation speed.
Keywords :
adders; area-time efficient modulo 2n+1 adders; diminished-1 modulo 2n+1 adders; sparse carry computation unit; Adders; Computer architecture; Delay; Finite wordlength effects; Microprocessors; Power demand; Proposals; Modulo $2^n+1$ addition; RNS; diminished-1 adder; parallel-prefix carry computation;
Conference_Titel :
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location :
Lixouri, Kefalonia
Print_ISBN :
978-1-4244-7321-2
DOI :
10.1109/ISVLSI.2010.35
