AES algorithm implementation - an efficient approach for sequential and pipeline architectures

We present an efficient implementation of the Rijndael cryptographic algorithm on FPGAs, which is a new advanced encryption standard (AES). The implementation of AES has been carried out in both sequential and pipeline architectures and we are able to compare the results as an area time trade-off. In sequential architecture, the design occupies 2744 CLB slices and achieves a throughput of 258.5 Mbit/s and there is no use of extra memory resources like FPGA BRAMS. On the other hand, our pipeline design occupies a total of 2136 CLB slices and achieved a throughput of 2868 Mbit/s. Both designs were realized on the VirtexE family of devices (XCV812). The performance figures achieved by our implementations are not only efficient in terms of throughput but also areas occupied by them are among the most economical reported to date.