DocumentCode
2091920
Title
BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
Author
Rahmani, Amir-Mohammad ; Liljeberg, Pasi ; Plosila, Juha ; Tenhunen, Hannu
Author_Institution
Turku Centre for Comput. Sci. (TUCS), Turku, Finland
fYear
2010
fDate
5-7 July 2010
Firstpage
452
Lastpage
453
Abstract
In this paper, a 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate area footprints of vertical interconnects. BBVCs, which can be dynamically self-configured to transmit flits in either direction, enable the system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer communication. By exploiting the high-speed nature of the vertical links in 3D ICs, this substitution indicates better bandwidth utilization, lower area footprint, and improved routability at each layer. Our results reveal that the proposed architecture helps to achieve up to 47% savings in TSV area footprint at the 65nm technology node.
Keywords
integrated circuit interconnections; network-on-chip; three-dimensional integrated circuits; 3D IC; BBVC-3D-NoC; bidirectional bisynchronous vertical channels; interlayer communication; vertical interconnects; Bandwidth; Computer architecture; Integrated circuit interconnections; Routing; Three dimensional displays; Through-silicon vias; Traffic control; 3D ICs; GALS; Networks-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on
Conference_Location
Lixouri, Kefalonia
Print_ISBN
978-1-4244-7321-2
Type
conf
DOI
10.1109/ISVLSI.2010.21
Filename
5572842
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