Title :
Switch-level timing models in the MOS simulator BRASIL
Author :
Warmers, H. ; Sass, D. ; Horneber, E.-H.
Author_Institution :
Inst. fuer Netzwerktheorie und Schaltungstech., Tech. Univ. Braunschweig, Germany
Abstract :
New timing models have been developed and implemented in the switch-level timing simulator BRASIL which are able to give fairly accurate signal waveforms. This enables the detection of faulty aspect ratios, dynamic hazards and races and timing faults caused by clock skew in NMOS and CMOS circuits. In contrast to most existing switch-level timing simulators the algorithm is not restricted to tree structures of the active subnetworks
Keywords :
CMOS integrated circuits; circuit analysis computing; CMOS; NMOS; clock skew; dynamic hazards; faulty aspect ratios; races; signal waveforms; switch level timing models; timing faults; Circuit faults; Circuit simulation; Clocks; Electrical fault detection; Fault detection; Hazards; MOS devices; Semiconductor device modeling; Timing; Tree data structures;
Conference_Titel :
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location :
Glasgow
Print_ISBN :
0-8186-2024-2
DOI :
10.1109/EDAC.1990.136711
