Title :
An FPGA design of low power LDPC decoder for high-speed wireless LAN
Author :
Kim, Min Hyuk ; Park, Tae Doo ; Kim, Chul Seong ; Jung, Ji Won
Author_Institution :
Korea Maritime Univ., Busan, South Korea
Abstract :
This paper proposes three kinds of simplified complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. Second, an early detection method for reducing the computational complexity is proposed. Finally, in order to support the high-speed systems, we implemented LDPC decoder using three algorithms by N=648, R=1/2. And the decoder runs at a clock speed of 10ns. Therefore we implemented the LDPC decoder with the decoding speed of 110 Mbps.
Keywords :
computational complexity; field programmable gate arrays; parity check codes; sequential decoding; wireless LAN; FPGA design; complexity-reduced algorithms; computational complexity; early detection method; high-speed systems; high-speed wireless LAN; low density parity check decoder; low-power LDPC decoder; sequential decoding; wireless local area networks; Clocks; Decoding; Ions; Parity check codes; Random access memory; Table lookup; World Wide Web;
Conference_Titel :
Communication Technology (ICCT), 2010 12th IEEE International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-6868-3
DOI :
10.1109/ICCT.2010.5688980
