• DocumentCode
    2092806
  • Title

    A New Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement with Attenuated Phase Shift Mask

  • Author

    Zhen Geng ; Zheng Shi ; Xiaolang Yan ; Kaisheng Luo

  • Author_Institution
    Institue of VLSI Design, Zhejiang Univ., Hangzhou, China
  • fYear
    2013
  • fDate
    16-18 Nov. 2013
  • Firstpage
    68
  • Lastpage
    73
  • Abstract
    Inverse lithography technology (ILT) is one of the promising resolution enhancement techniques (RET), as the advanced integrated circuits (IC) technology nodes still use the 193nm light source. Among all the algorithms for ILT, the level-set-based ILT (LSB-ILT) is a feasible choice with good production result in practice. However, existing ILT algorithms optimize mask at nominal process condition without giving sufficient attention to the process variations, and thus the optimized masks show poor performance with focus and dose variations. In this paper, we put forward a new LSB-ILT algorithm for process robustness improvement with attenuated Phase Shift Mask (att-PSM) which is extensively used in the semiconductor foundries. In order to account for the process variations in the optimization, we adopt a new form of the cost function by adding the objective function of process variation band (PV band) to the nominal cost. The test patterns are from the M1 layer of a 28nm layout. Experimental results show that our new algorithm has a larger process window (PW) and reduces the process manufacturability index (PMI) by 41.37% compared with the LSB-ILT algorithm without PV band consideration.
  • Keywords
    lithography; phase shifting masks; LSB-ILT algorithm; M1 layer; PMI; RET; advanced integrated circuits technology nodes; att-PSM; attenuated phase shift mask; cost function; inverse lithography technology; level-set-based ILT; nominal cost; process manufacturability index; process robustness improvement; process variation band; process window; resolution enhancement techniques; semiconductor foundries; size 28 nm; test patterns; Algorithm design and analysis; Cost function; Layout; Linear programming; Lithography; Mathematical model; Robustness; inverse lithography technology; level set; process variation band; process window;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design and Computer Graphics (CAD/Graphics), 2013 International Conference on
  • Conference_Location
    Guangzhou
  • Type

    conf

  • DOI
    10.1109/CADGraphics.2013.16
  • Filename
    6814979