Title :
A CMOS 20 MHz 8 bit 50 mW ADC for mixed analog/digital ASICs
Author :
Tsuji, Kazuhiro ; Sugiyama, Hisashi ; Sugawa, Naoki
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A cascaded two-stage comparator was used to develop a 20-MHz 8-b analog-to-digital converter (ADC) with high power supply rejection ratio (40 dB) and low power consumption (50 mW). Adopting a bias current generator, power consumption became less dependent on power supply voltage and process variation without external trimming. By applying subranging architecture, the core size was drastically reduced (2.9 mm 2 using 0.8-μm CMOS technology). As a result, the total performance of the ADC is suitable for a mixed analog/digital ASIC (application-specific integrated circuit) core
Keywords :
CMOS integrated circuits; analogue-digital conversion; application specific integrated circuits; 0.8 micron; 20 MHz; 50 mW; A/D convertor; ADC; CMOS technology; application-specific integrated circuit; bias current generator; cascaded two-stage comparator; low power consumption; mixed analog/digital ASICs; power supply rejection ratio; subranging architecture; Application specific integrated circuits; CMOS analog integrated circuits; CMOS digital integrated circuits; Choppers; Circuit noise; Energy consumption; Inverters; Logic; Timing; Voltage control;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164178
