An Efficient Zero-Aliasing Space Compactor Based on Elementary Gates Combined with XOR Gates

Space compactor is usually applied in DfT design to compact the output response data in order to reduce testing time and storage. We propose an efficient method to implement a tree-like zero-aliasing space compactor with elementary logic gates combined with the XOR gates. Based on the fault-output response table, our method selects appropriate logic gates to combine the outputs of the CUT with remaining most D and D´. When faults are concealed in the table, all other available test patterns for these faults will be checked to determine whether the faults can be detected. No ATPG is involved in the search of new test patterns for the covered faults during compaction. To reduce the hardware overhead, the XOR gate is only used when all other elementary gates fail to achieve further compaction. When compared with existing ATPG-based compactors, our proposed compactor can achieve similar compaction ratio with similar hardware cost. However, our method will be much more efficient because it does not perform the time-consuming ATPG procedure. When compared with other XOR-based compactors, our method can achieve higher compaction ratio with smaller area overhead.