• DocumentCode
    2092942
  • Title

    Congestion driven quadratic placement

  • Author

    Parakh, Phiroze N. ; Brown, Richard B. ; Sakallah, Karem A.

  • Author_Institution
    Michigan Univ., Ann Arbor, MI, USA
  • fYear
    1998
  • fDate
    19-19 June 1998
  • Firstpage
    275
  • Lastpage
    278
  • Abstract
    This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.
  • Keywords
    VLSI; circuit layout CAD; congestion driven quadratic placement; growth matrix; line-probe heuristics; quadratic placement; region-based routing graphs; routing analysis; wireability; wiring congestion; Design automation; Partitioning algorithms; Permission; Pins; Quality management; Resource management; Routing; Very large scale integration; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1998. Proceedings
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-89791-964-5
  • Type

    conf

  • Filename
    724481