Title :
SUNNY-RISC: a VLSI RISC micro-architecture
Author :
Chen, I. ; Goshtasbi, J. ; Hsu, S. ; Strauss, M. ; Wang, T. ; Delgado-Frias, J.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
A VLSI reduced instruction set computer (RISC) microarchitecture called SUNY-RISC is described. The SUNY-RISC processor is a 16-bit microarchitecture. Most of the instructions are register to register. This approach results in fast execution and simple control logic. SUNY-RISC has some similarities with RISC approaches; however, this machine introduces some new features: support for subroutine call and return and instructions broken into several small steps. The technology used is 1 micron CMOS p-well. SUNY-RISC implements 38 instructions. Some instructions require a double word, for instance load register direct and call. The subsystems described are the arithmetic logic unit and shifter, the internal clock, the constant generator, and special purpose registers
Keywords :
CMOS integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; 16 bit; 16 bit processor; ALU; CMOS p-well; RISC micro-architecture; SUNY-RISC; VLSI reduced instruction set computer; arithmetic logic unit; arithmetic shifter; constant generator; double word; fast execution; internal clock; simple control logic; special purpose registers; subroutine call; subroutine return; Algorithms; Arithmetic; CMOS logic circuits; CMOS technology; Clocks; Computer aided instruction; Microarchitecture; Reduced instruction set computing; Registers; Very large scale integration;
Conference_Titel :
Southern Tier Technical Conference, 1990., Proceedings of the 1990 IEEE
Conference_Location :
Binghamton, NY
DOI :
10.1109/STIER.1990.324641
