DocumentCode :
2093087
Title :
A fast adder design using signed-digit numbers and ternary logic
Author :
Rajashekhara, T. ; Chen, I-Shi
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
fYear :
1990
fDate :
32988
Firstpage :
187
Lastpage :
194
Abstract :
The advantage of carry free addition offered by signed-digit numbers is exploited in designing a fast adder circuit. Signed-digit numbers with radix 2 and digit set {-1,0,1}, called redundant binary signed-digit (RBSD) numbers, are used in the design. Ternary logic circuits using an MOS/CMOS combination are employed. The ternary logic and RBSD number system complement each other well because one ternary bit can support one RBSD digit. This provides an advantage over using binary logic where more than one bit would be needed to support one RBSD digit. While the RBSD number system offers faster add times because of carry free addition, ternary logic offers reduced circuit complexity in terms of both transistor count and interconnections. All circuit implementations were simulated and verified for satisfactory performance using SPICE software on a SUN workstation
Keywords :
adders; digital arithmetic; logic CAD; ternary logic; MOS/CMOS combination; RBSD digit; RBSD number system; SPICE software; SUN workstation; carry free addition; fast adder design; radix 2; reduced circuit complexity; redundant binary signed-digit; signed-digit numbers; ternary bit; ternary logic; Adders; CMOS logic circuits; Circuit simulation; Complexity theory; Integrated circuit interconnections; Multivalued logic; SPICE; Software performance; Sun; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southern Tier Technical Conference, 1990., Proceedings of the 1990 IEEE
Conference_Location :
Binghamton, NY
Type :
conf
DOI :
10.1109/STIER.1990.324644
Filename :
324644
Link To Document :
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