Title :
Signature analyzers in built-in self-test circuits: a perspective
Author :
Rajashekhara, T.N.
Author_Institution :
Dept. of Electr. Eng., State Univ. of New York, Binghamton, NY, USA
Abstract :
The test response compression technique using signature analyzers or linear feedback shift registers (LFSRs) is discussed and some representative built-in self-test (BIST) designs which make use of LFSRs are presented. Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using LFSRs. The input to the LFSR is received from the output of a multiple input single output circuit under test (CUT). The structure and characteristics of LFSRs including a simplified mathematical analysis showing the confidence level in detecting faults are discussed. Some BIST design examples which include a programmable logic array, semiconductor memory, and a microcomputer are presented
Keywords :
built-in self test; integrated memory circuits; logic analysers; logic arrays; logic testing; microprocessor chips; shift registers; BIST design; CRC; built-in self-test circuits; confidence level; cyclic redundancy checking; fault detection; linear feedback shift registers; microcomputer; multiple input single output; programmable logic array; semiconductor memory; signature analyzers; test response compression technique; Automatic testing; Built-in self-test; Circuit testing; Cyclic redundancy check; Electrical fault detection; Fault detection; Hardware; Linear feedback shift registers; Mathematical analysis; Programmable logic arrays;
Conference_Titel :
Southern Tier Technical Conference, 1990., Proceedings of the 1990 IEEE
Conference_Location :
Binghamton, NY
DOI :
10.1109/STIER.1990.324654
