• DocumentCode
    2093412
  • Title

    Cell based performance optimization of combinational circuits

  • Author

    Hinsberger, Uwe ; Kolla, Reiner

  • Author_Institution
    Fachbereich Inf., Univ. de Saarlandes, Saarbrucken, Germany
  • fYear
    1990
  • fDate
    12-15 Mar 1990
  • Firstpage
    594
  • Lastpage
    599
  • Abstract
    Performance optimization, i.e. the problem of finding an optimal investment of transistor area which meets given delay constraints, is considered from an abstract, cell based point of view which allows only solutions within a discrete solution space of coarse granularity. The main advantages of this problem modelling are the independence of the methods from concrete delay modelling (and thus from technology) and the applicability to even very restrictive design styles (as for example gate arrays or sea of gates). The paper contains a classification of the computational complexity of the performance optimization problem as well as efficient algorithms (where they exist), heuristics and experimental results
  • Keywords
    combinatorial circuits; computational complexity; logic CAD; optimisation; cell based performance optimisation; coarse granularity; combinational circuits; computational complexity; gate arrays; heuristics; sea of gates; transistor area; Boolean functions; Combinational circuits; Concrete; Delay; Impedance; Libraries; MOSFETs; Optimization; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990., EDAC. Proceedings of the European
  • Conference_Location
    Glasgow
  • Print_ISBN
    0-8186-2024-2
  • Type

    conf

  • DOI
    10.1109/EDAC.1990.136716
  • Filename
    136716