Title :
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
Author :
Juinn-Dar Huang ; Jing-Yang Jou ; Wen-Zen Shen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.
Keywords :
circuit optimisation; field programmable gate arrays; iterative methods; logic CAD; table lookup; LUT-based FPGA technology mapping; area-optimized performance-considered initial network; iterative algorithm; iterative area; mapping solutions; modified area optimization technique; performance trade-off algorithm; timing driven FPGA synthesis; Central Processing Unit; Circuits; Iterative algorithms; Performance evaluation; Sorting; Table lookup;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.568903