Architecture Design and VLSI Implementation of the Re-conf1gurable 2-D CAT/ICAT Chip for the Applications of Image Compression

Architecture design and VLSI implementation of the re-configurable 2-D CAT/ICAT chip for developing the CAT wavelets-based image coding system is presented in this paper. To facilitate the development of this CAT/ICAT chip, we firstly develop the evolution of CA to produce orthogonal 1-D CA bases; then we use the canonical product circuit to produce 2-D CA bases; finally, it utilizes input data and 2-D CA bases to produce 2-D CAT/ICAT coefficients. In order to enhance the flexibility of applications, we developed the re-configurable 2-D CAT/ICAT circuit to make the proposed chip to produce 2-D 4 x 4, 8 x 8, and 16 x 16 CAT/ICAT coefficients. Throughputs of the 2-D 8 x 8, and 16 x 16 CAT/ICAT coefficients are same as that of 2-D 4 x 4 CAT/ICAT coefficients due to the proposed re-configurable 2-D CAT/ICAT chip has highly parallel processing property. We have accomplished the circuit synthesis using the SYNOPSYS tolls with the UMC 0.18 um Cell-library. The chip size was 12.888 mm , and the maximum operation frequency was 111MHz with 851mW total dynamic power. It shows that the architecture of the proposed re-configurable 2-D CAT/ICAT chip is suitable for VLSI realization .