CLIMATE (chip-level intertwined metal and active temperature estimator)

ULSI interconnect temperature is critical for electromigration risk assessment because of the exponential dependence of lifetime on temperature and for performance issues such as timing which are sensitive to temperature-dependent resistance. Steady state wire temperature is a function of Joule self-heating within the wire, heat conducted along the wire, and heat coupled from the active devices and other nearby wires through the dielectric. Chip-level estimates of wire temperatures for HP´s EV79 microprocessor require rapid processing of vast circuits and thus detailed physical calculations such as those based on 3D finite element models (FEM) are inappropriate. However, temperatures on such large devices can be accurately estimated at the resolution of individual segments of wire as extracted by geometric processing of the layout given each segment´s relevant geometry, connectivity to other segments, current I/sub rms/, and the thermal conductances G/sup lat/ between them.