Title :
What´s between simulation and formal verification?
Author_Institution :
Stanford Univ., CA, USA
Abstract :
This embedded tutorial surveys some possibilities for verification techniques that combine conventional simulation and ideas, techniques, and algorithms from formal verification, to obtain better functional test coverage of large designs.
Keywords :
formal verification; logic testing; functional test coverage; large designs; simulation; verification techniques; Algorithm design and analysis; Analytical models; Computational modeling; Delay effects; Emulation; Formal verification; Humans; Permission; Testing; Time to market;
Conference_Titel :
Design Automation Conference, 1998. Proceedings
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-89791-964-5
