Title :
Performance analysis of multi-dimensional packet classification on programmable network processors
Author :
Srinivasan, Deepa ; Feng, Wu-Chand
Author_Institution :
RTP, IBM Corp., NC, USA
Abstract :
Multi-field packet classification is frequently performed by network devices such as edge routers and firewalls - such devices can utilize programmable network processors to perform this computation-intensive task at nearly line speeds. The architectures of programmable network processors are typically highly parallel and a single algorithm can be mapped in different ways onto the hardware. We study the performance of two different design mappings of the bit vector packet classification algorithm on the Intel® IXP1200 network processor. We show that: (i) overall, parallel mapping has a better packet processing rate (25% more) than pipelined mapping; (ii) in parallel mapping, a processing element´s utilization can be considerably affected by code complexity, in terms of branching, because of significant time wasted (as much as 40% more) due to aborting instruction execution pipelines; (iii) in pipelined mapping, multiple memory reads per packet can lower the overall performance.
Keywords :
microprocessor chips; packet switching; parallel architectures; pipeline processing; program processors; Intel IXP1200 network processor; bit vector packet classification algorithm; code complexity; edge routers; firewalls; instruction execution pipeline; multi-field packet classification; multidimensional packet classification; parallel architectures; parallel mapping; pipelined mapping; programmable network processors; Algorithm design and analysis; Classification algorithms; Computer architecture; Computer networks; Hardware; Image edge detection; Intrusion detection; Performance analysis; Pipelines; Yarn;
Conference_Titel :
Local Computer Networks, 2004. 29th Annual IEEE International Conference on
Print_ISBN :
0-7695-2260-2
DOI :
10.1109/LCN.2004.94