Investigation of thermal breakdown mechanism in 0. 13 /spl mu/m technology ggNMOS under ESD conditions

Transient device simulations reproducing conditions similar to Electro-Static Discharge (ESD) conditions have been performed for the entire safe operating area (SOA) of a 0.13 /spl mu/m technology, ground-gated N-channel Metal-Oxide-Semiconductor (ggNMOS) transistor up to 2/sup nd/ breakdown, using a set of macroscopic physical models related to previous studies implemented in MEDICI. The simulations results indicate the potential influence of a source-end mechanism of destruction, in addition to the previously reported drain-end avalanche generation of electron-hole pairs and subsequent thermal runaway in the proximity of the carriers generation spot as a result of the large carrier density. Under dynamic conditions and with non-zero contact resistance, thermal runway is also observed on the source-side of the device indicating that, for values of the contact resistance on the order of 5.4e/sup -6/ Ohms-cm/sup 2/, substantial damage can occur at the source end. The simulation results are in qualitative agreement with experimental results where it is observed that, after electrical and subsequent thermal runaway, damage is localized not only at the drain region but also at the source region of the device. Thus, the ESD related destruction of a 0.13 /spl mu/m gate ggNMOS may not be the result of a single destruction mechanism, but the consequence of coupled events, depending on the design characteristics of a particular device.