Simulation of number of pulses to breakdown during TLP for ESD testing

Author

Matsuzawa, Kazuya ; Satake, Hideki ; Sutou, Chie ; Kawashima, Hirobumi

Author_Institution

Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

129

Lastpage

132

Abstract

The breakdown characteristics of the gate insulator of nMOSFETs during transmission line pulsing for electrostatic discharge testing is evaluated by using device simulations. Experimental data for the gate bias and gate oxide thickness dependences of the number of pulses to breakdown are reproduced by adopting the anode-hole-injection model. The polarity of the gate bias dependence of the breakdown characteristics can be explained by the depletion of the gate electrode.

Keywords

MOSFET; electrostatic discharge; semiconductor device models; semiconductor device reliability; MOSFET; anode-hole-injection model; breakdown characteristics; device simulations; electrostatic discharge testing; gate bias; gate insulator; gate oxide thickness; transmission line pulsing; Charge carrier processes; Circuit simulation; Current density; Electric breakdown; Electrostatic discharge; Impact ionization; Insulation; Insulator testing; Semiconductor device testing; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233654

Filename

1233654