DocumentCode
2096233
Title
Delay-optimal technology mapping by DAG covering
Author
Kukimoto, Yuji ; Brayton, Robert K. ; Sawkar, Prashant
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1998
fDate
19-19 June 1998
Firstpage
348
Lastpage
351
Abstract
We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach.
Keywords
circuit layout CAD; logic CAD; DAGs; delay improvement; delay minimization; library-based designs; minimal-delay; minimal-delay technology mapping; technology mapping; Algorithm design and analysis; Circuits; Delay; Design automation; Dynamic programming; Field programmable gate arrays; Laboratories; Permission; Tree graphs; Vegetation mapping;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724495
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