A FinFET design based on three-dimensional process and device simulations

Author

Kondo, Masaki ; Katsumata, Ryota ; Hideaki, A. ; Hamamoto, Takeshi ; Ito, Sanae ; Aoki, Nobutoshi ; Wada, Tetsunori

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

179

Lastpage

182

Abstract

In this paper, a practical design method of a FinFET is presented with :in example of a scaled DRAM device. The electric properties of the FinFET are analyzed by means of three-dimensional process and device simulations. The analysis reveals that the short channel effects depend strongly on not only the thickness but also the taper angle of the silicon pillar. The device is optimized successfully assuming the tapered shape for the silicon pillar. The simulated characteristics (0.1fA off-leak current and 62/spl mu/A drive current per unit cell @ 85C) well agree with experimental results.

Keywords

DRAM chips; field effect transistors; semiconductor device models; 62 muA; FinFET design; Si pillar; drive current per unit cell; electric properties; off-leak current; scaled DRAM device; short channel effects; taper angle; three-dimensional process and device simulations; Controllability; Degradation; Electrodes; FinFETs; Indium tin oxide; Poisson equations; Random access memory; Shape; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233666

Filename

1233666