DocumentCode :
2096385
Title :
Grain boundary effects on subthreshold behaviour in single grain boundary nano-TFTs
Author :
Walker, Philip ; Mizuta, Hiroshi ; Uno, Shigeyasu ; Furuta, Yoshikazu
Author_Institution :
Microelectron. Res. Centre, Cambridge, UK
fYear :
2003
fDate :
3-5 Sept. 2003
Firstpage :
207
Lastpage :
210
Abstract :
A simulation model for deep trap states at grain boundaries in Poly-Si TFTs is developed. The model is used for simulation of single GB TFT devices with sub micron channel lengths. The transport physics is clarified and it is found that in short channel devices (L/sub eff/<100 nm) the single GB TFT shows improved subthreshold behaviour compared to its SOI equivalent.
Keywords :
deep levels; electron traps; elemental semiconductors; grain boundaries; semiconductor device models; silicon; thin film transistors; 100 nm; deep trap states; grain boundary effects; micron channel lengths; short channel devices; single grain boundary nano-TFTs; subthreshold behaviour; transport physics; Active matrix liquid crystal displays; Charge carrier processes; Crystallization; Current density; Electron traps; Grain boundaries; Grain size; Laboratories; Poisson equations; Thin film transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-7803-7826-1
Type :
conf
DOI :
10.1109/SISPAD.2003.1233673
Filename :
1233673
Link To Document :
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