DocumentCode
2096538
Title
A novel sub-20 nm depletion-mode double-gate (DMDG) FET
Author
Krishnamohan, Tejas ; Krivokapic, Zoran ; Saraswat, Krishna C.
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA, USA
fYear
2003
fDate
3-5 Sept. 2003
Firstpage
243
Lastpage
246
Abstract
We present a novel Depletion-Mode Double-Gate (DMDG) FET. As opposed to the conventional, un-doped body, double-gate MOSFETs, the DMDG device confines the carriers to the center of the device for all applied gate voltages. The device exhibits high mobility due to the carrier confinement in the very low E-field region in the center of the device. Simulations show very high I/sub on//I/sub off/ ratios (NMOS=2.07 mA/25 nA, PMOS=1.02 mA/0.98 nA), excellent sub-threshold slopes and Fan-Out-Four (FO4) delays under 5.5 ps for 15 nm gate lengths.
Keywords
MOSFET; carrier density; carrier mobility; semiconductor device models; 20 nm; 5.5 ps; Fan-Out-Four delays; applied gate voltages; carrier confinement; double-gate MOSFETs; high mobility; sub-20 nm depletion-mode double-gate FET; sub-threshold slopes; Backscatter; Carrier confinement; Degradation; Delay; Double-gate FETs; Electrostatics; MOSFETs; Scattering; Silicon; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
Conference_Location
Boston, MA, USA
Print_ISBN
0-7803-7826-1
Type
conf
DOI
10.1109/SISPAD.2003.1233682
Filename
1233682
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