An investigation of the electron tunneling leakage current through ultrathin oxides/high-k gate stacks at inversion conditions

Author

Govoreanu, Bogdan ; Blomme, Pieter ; Henson, Kirklen ; Van Houdt, Jan ; De Meyer, Kristin

Author_Institution

SPDT Div., IMEC, Leuven, Belgium

fYear

2003

fDate

3-5 Sept. 2003

Firstpage

287

Lastpage

290

Abstract

An efficient yet accurate model is used for investigating tunneling of minority carriers from the inversion layer of ultrathin MOSFET structures. The model is derived from the concept of the quasibound states lifetimes, which are calculated using a transfer matrix method based on Airy functions. Comparison with experimental data is provided. Performance of high-k materials is discussed and an investigation of their scalability for future CMOS technology nodes is carried out.

Keywords

CMOS integrated circuits; MOSFET; interface states; inversion layers; leakage currents; semiconductor device models; transfer function matrices; tunnelling; Airy functions; CMOS technology nodes; electron tunneling leakage current; high-k materials; inversion conditions; inversion layer; minority carriers; quasibound state lifetimes; scalability; transfer matrix method; tunneling; ultrathin MOSFET structures; ultrathin oxide/high-k gate stacks; CMOS technology; Electrons; Gate leakage; High K dielectric materials; High-K gate dielectrics; Leakage current; Potential well; Probability; Scalability; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on

Conference_Location

Boston, MA, USA

Print_ISBN

0-7803-7826-1

Type

conf

DOI

10.1109/SISPAD.2003.1233693

Filename

1233693