DocumentCode
2096841
Title
Effects of gate-to-body tunneling current on PD/SOI CMOS latches
Author
Chuang, C.T. ; Puri, R.
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2003
fDate
3-5 Sept. 2003
Firstpage
291
Lastpage
294
Abstract
This paper presents a detailed study on the effect of gate-to-body tunneling current on PD/SOI CMOS latches. The physical mechanism and its impact on the initial quiescent states and performance of the latches are analyzed. It is shown that the effect on latch setup time is particularly significant due to the compounding effect of the master-slave configuration.
Keywords
CMOS digital integrated circuits; elemental semiconductors; flip-flops; silicon; silicon-on-insulator; tunnelling; PD/SOI CMOS latches; Si-SiO/sub 2/; gate-to-body tunneling current; initial quiescent states; latch setup time; master-slave configuration; physical mechanism; Clocks; Delay; Feedback; Inverters; Latches; Master-slave; Partial discharges; Performance analysis; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003. International Conference on
Conference_Location
Boston, MA, USA
Print_ISBN
0-7803-7826-1
Type
conf
DOI
10.1109/SISPAD.2003.1233694
Filename
1233694
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