A new power distribution strategy for area array bonded ICs and packages of future deep sub-micron ULSI

Signal and power distribution of deep sub-micron ULSI ICs compete for on-chip wiring resources because of increasing chip power dissipation, reduced supply voltage, increased signal wiring demand, higher operating frequency and interconnect delay limitations. We propose a novel cascaded power/ground ring approach for on-chip power distribution, which simultaneously addresses power and signal distribution. Three power distribution approaches have been analyzed and compared. It will be shown that substantial packaging support for on-chip power distribution is imperative for future deep sub-micron ULSI IC´s. Simulation results indicate that the cascaded power/ground ring power distribution approach reduces total on-chip metal interconnect levels compared to conventional power distribution methods, while meeting both signal and power distribution goals. The benefit of reducing the total on-chip metal interconnect levels carries significant implications for reducing manufacturing cost and the design of future deep sub-micron ASIC and microprocessor IC´s and their packages