Laboratory measurement of voltage drop at an integrated circuit core due to parasitic inductances

The design of the power distribution systems (PDS) for an integrated circuit limits its performance due to the simultaneous switching noise (SSN) generated by the voltage drop across the system´s parasitic inductances. This paper presents a method to make laboratory measurements that can characterize the instantaneous current draw of a sample integrated circuit (IC). This behavioral model is used in conjunction with a SPICE modeling of the PDS to bound the voltage drop seen at the IC´s core. This characterization can then be used by IC packaging and PCB designers to determine optimum PDS design strategies.